1. Field of the Invention
The present invention relates generally to a nonvolatile memory device and, more particularly, to a ferroelectric random access memory (FRAM) using ferroelectric capacitance memory cells and methods of driving the same.
A claim of priority is made to Korean Patent Application No. 2005-112453 filed on Nov. 23, 2005, the subject matter of which is incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices are generally categorized into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices are divided into dynamic random access memories and static random access memories. While the volatile semiconductor memory devices have fast read and write operation rates, they loose stored data when an external power supply is cut off. On the other hand, the nonvolatile semiconductor memory devices can maintain stored data even when an external power supply is cut off. Therefore, the nonvolatile semiconductor memory devices are used in applications where there is a requirement for storing data in the absence of an external power supply.
Non-volatile memory devices may come in a variety of forms. These may include, for example, ferroelectric random access memories (FRAMs) and flash memories. Both FRAMs and flash memories are capable of executing high-rate data operations. However, the FRAMs have certain features that may make them more suitable for some applications. These features include, for example, low power dissipation and good impact endurance. The above-mentioned features may make, FRAMs usable as a main memory for various portable electronic devices.
FIG. 1 is a circuit diagram showing a conventional FRAM cell MC. Referring to FIG. 1, the FRAM cell MC includes one switch transistor Tr and one ferroelectric capacitor Cf. In cell MC, one terminal of the switch transistor Tr is connected to a bit line BL and another terminal is connected to one electrode of the ferroelectric capacitor Cf. Furthermore, the switch transistor Tr is gated to a word line MWL. The other electrode of the ferroelectric capacitor Tr is connected to a plate line MPL.
The FRAM cell MC stores logic states based on an electric polarization of the ferroelectric capacitor Cf. Specifically, a ferroelectric layer like a PZT (lead zirconate titanate) layer is formed between both electrodes of the ferroelectric capacitor Cf. Furthermore, when a voltage is applied to the electrodes (or plates) of the ferroelectric capacitor Cf, the ferroelectric layer is polarized along a direction of an electric field. At this time, a switching threshold for changing the polarization state of the ferroelectric capacitor Cf is called “a coercive voltage”. In addition, the ferroelectric capacitor Cf is characterized by a hysteresis phenomenon. Moreover, a current corresponding to the polarization flows through the capacitor Cf.
When the voltage applied to the ferroelectric capacitor Cf is higher than the coercive voltage, the polarization state of the ferroelectric capacitor Cf changes according to a polarity of the applied voltage. In addition, the polarization state of the ferroelectric capacitor Cf is maintained as it is after the applied voltage is interrupted. This maintenance of the polarization state of the capacitor Cf despite the absence of the applied voltage allows for the FRAM to be used as a nonvolatile memory device.
Furthermore, the ferroelectric capacitor Cf has a high capacitance because of its high permittivity. In addition, ferroelectric capacitors are typically connected to one plate line MPL (as shown in FIG. 1). Therefore, because of the high capacitance of the capacitor Cf, a pulse signal applied to the plate line MPL is delayed for a long time (or has a long raising time). This delay of the pulse signal may degrade an operation rate of FRAM devices. There is therefore a need for methods for improving the operation rates of the FRAM devices.
Data stored in the FRAM cell MC is read out as follows. First, a voltage is applied to both electrodes of the ferroelectric capacitor Cf of the FRAM cell MC. Then, the bit line BL connected to the memory MC is sensed to find a variation in the amount of electrons induced thereto. A reference voltage generator is required to sense the variation in the amount of electrons arising in the bit line BL (i.e., a voltage variation of the bit line BL). This reference voltage generator generates a reference voltage Vref whose intermediate level corresponds to data “1” and whose lower level corresponds to data “0”. Generally, the reference voltage Vref is generated by a reference cell having a ferroelectric capacitor Cf. In particular, the reference cell has the same characteristics as the FRAM cell MC.
A polarization of the ferroelectric capacitor in the memory cell MC is difficult to sense because an electrical field/polarization characteristic loop (i.e., a hysteresis loop) changes with time. Specifically, the hysteresis loop fades as time elapses. This is because of the non-reversibility occurring in a part of the ferroelectric layer in an electric field/polarization circulation. Furthermore, a voltage of the bit line BL connected to the ferroelectric memory cell MC also changes with time. The variation of the bit line voltage depending on time is described hereinafter.
FIG. 2 illustrates a variation in the amount of the induced bit line voltages with respect to time for each data state. Referring to FIG. 2, an increase ratio of a bit line voltage corresponding to data “1” (D1) is different from a decrease ratio of a bit line voltage corresponding to data “0” (D0). Therefore, when a predetermined time t1 elapses, sense margins MD 1 and MD0 increase respectively according to different ratios. Specifically, the sense margin MD1 is a difference between the bit line voltage D1 corresponding to data “1” and the reference voltage Vref. Similarly, the sense margin MD0 is a difference between the bit line voltage D0 corresponding to data “0” and the reference voltage Vref. Therefore, after the predetermined time t1, the reference voltage Vref may not have the same value as the intermediate bit line voltage D1 corresponding to the data “1” and the bit line voltage D0 corresponding to the data “0”. This difference between the reference voltage Vref and the bit line voltages D1 and D0 may degrade the reliability of the FRAM. Thus, there exist problems pertaining to the reliability and stability of FRAM.
The present disclosure is directed towards overcoming one or more problems associated with the prior art FRAM devices.